In the field of high-speed serial data communications, e.g., with regard to a universal serial bus, clock and data recovery (CDR) circuits are often used. In many applications, high-speed data streams are sent without an accompanying clock signal. The CDR on the receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream. However, data jitter and phase error between clock and data can cause glitches (a pulse too small to trigger a flip flop or a logic gate properly) in recovered clock and data errors in the CDR. Furthermore, integrated circuit process deviations, operating temperature, and power supply variations can also have a negative impact on sampling window width and thus on the recovered clock and data accuracy.